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april 2012 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 FSL116LR ? green mode fairchild power switch (fps?) FSL116LR green mode fairchild power switch (fps?) features ? internal avalanche-rugged sensefet (650v) ? under 50mw standby power consumption at 265vac, no-load condition with burst mode ? precision fixed operating frequency with frequency modulation for attenuating emi ? internal startup circuit ? built-in soft-start: 20ms ? pulse-by-pulse current limiting ? various protections: over-voltage protection (ovp), overload protection (olp), output-short protection (osp), abnormal over-current protection (aocp), internal thermal shutdown function with hysteresis (tsd) ? auto-restart mode ? under-voltage lockout (uvlo) ? low operating current: 1.8ma ? adjustable peak current limit applications ? smps for vcr, stb, dvd, & dvcd players ? smps for home appliance ? adapter related resources ? an-4137 ? design guidelines for off-line flyback converters using fps? ? an-4141 ? troubleshooting and design tips for fairchild power switch (fps?) flyback applications ? an-4147 ? design guidelines for rcd snubber of flyback ? fairchild power supply webdesigner ? flyback design & simulation - in minutes at no expense description the FSL116LR integrated pu lse width modulator (pwm) and sensefet is specifically designed for high- performance offline switch-mode power supplies (smps) with minimal external components. FSL116LR includes integrated high- voltage power switching regulators that comb ine an avalanche-rugged sensefet with a current-mode pwm control block. the integrated pwm controller includes: under-voltage lockout (uvlo) protec tion, leading-edge blanking (leb), a frequency generator for emi attenuation, an optimized gate turn-on/turn-off driver, thermal shutdown (tsd) protec tion, and temperature- compensated precision current sources for loop compensation and fault prot ection circuitry. the FSL116LR offers good soft-start performance. when compared to a discrete mo sfet and controller or rcc switching converter solution, the FSL116LR reduces total component count, design size, and weight; while increasing efficiency, productivity, and system reliability. this device provides a basic platform that is well suited for the design of cost-effective flyback converters. maximum output power (1) 230v ac 15% (2) 85-265v ac adapter (3) open frame adapter (3) open frame 11w 16w 10w 14w notes: 1. the junction temperatur e can limit the maximum output power. 2. 230v ac or 100/115v ac with doubler. 3. typical continuous pow er in a non-ventilated enclosed adapter measured at 50 c ambient. ordering information part number operating temperature range top mark package packing method FSL116LR -40 to 105c FSL116LR 8-lead, dual inline package (dip) rail
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 2 FSL116LR ? green mode fairchild power switch (fps?) typical application diagram figure 1. typical application internal block diagram 8v/12v 2 6,7,8 1 3 v ref inte rna l bias s q q r osc v cc i delay i fb v sd tsd v ovp v cc v ao c p s q q r r 2.5r v cc good v cc drai n v fb gnd aocp gate driver 5 v str i ch v cc good v burl /v burh leb pwm 4 i pk soft start random frequency generator osp on-time detector v cc figure 2. internal block diagram
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 3 FSL116LR ? green mode fairchild power switch (fps?) pin configuration figure 3. pin configuration pin definitions pin # name description 1 gnd ground . sensefet source terminal on the prim ary side and internal control ground. 2 v cc positive supply voltage input . although connected to an auxiliary transformer winding, current is supplied from pin 5 (v str ) via an internal switch during startup ( see figure 2) . once v cc reaches the uvlo upper threshold (12v), the internal startup switch opens and device power is supplied via the auxiliary transformer winding. 3 v fb feedback voltage . the non-inverting input to the pwm comparator, it has a 0.4ma current source connected internally, while a capacit or and opto-coupler are typically connected externally. there is a delay while charging external capacitor c fb from 2.4v to 6v using an internal 5a current source. this delay prevent s false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. 4 i pk peak current limit . adjusts the peak current limit of the sensefet. the feedback 0.4ma current source is diverted to the par allel combination of an internal 6k ? resistor and any external resistor to gnd on this pi n to determine the peak current limit. 5 v str startup . connected to the rectified ac line voltage s ource. at startup, the internal switch supplies internal bias and charges an exte rnal storage capacitor placed between the v cc pin and ground. once v cc reaches 12v, the internal switch is opened. 6, 7, 8 drain drain . designed to connect directly to the prim ary lead of the transformer and capable of switching a maximum of 650v. minimizing the lengt h of the trace connecti ng these pins to the transformer decreases leakage inductance.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 4 FSL116LR ? green mode fairchild power switch (fps?) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. t j = 25c, unless otherwise specified. symbol parameter min. max. unit v str v str pin voltage -0.3 650.0 v v ds drain pin voltage -0.3 650.0 v v cc supply voltage 26 v v fb feedback voltage range -0.3 12.0 v i d continuous drain current 1 a i dm drain current pulsed (4) 4 a e as single pulsed avalanche energy (5) 38 mj p d total power dissipation 1.5 w t j operating junction temperat ure internally limited c t a operating ambient te mperature -40 +105 c t stg storage temperature -55 +150 c esd human body model, jesd22-a114 (6) 5 kv charged device model, jesd22-c101 (6) 2 ja junction-to-ambient thermal resistance (7,8) 80 c/w jc junction-to-case thermal resistance (7,9) 19 c/w jt junction-to-top thermal resistance (7,10) 33.7 c/w notes: 4. repetitive rating: pulse width limit ed by maximum junction temperature. 5. l=30mh, starting t j =25c. 6. meets jedec standards j esd 22-a114 and jesd 22-c101. 7. all items are tested with the standards jesd 51-2 and jesd 51-10. 8. ja free-standing, with no heat-sin k, under natural convection. 9. jc junction-to-lead thermal characteristics under ja test condition. t c is measured on the source #7 pin closed to plastic interface for ja thermo-couple mounted on soldering. 10. jt junction-to-top of thermal characteristic under ja test condition. t t is measured on top of package. thermo- couple is mounted in epoxy glue.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 5 FSL116LR ? green mode fairchild power switch (fps?) electrical characteristics t a = 25 c unless otherwise specified. symbol parameter conditions min. typ. max. units sensefet section bv dss drain-source breakdown voltage v cc = 0v, i d = 250a 650 v i dss zero gate voltage drain current v ds = 650v, v gs = 0v 250 a r ds(on) drain-source on-state resistance v gs = 10v, v gs = 0v, t c = 25c 7.3 10.0 ? c iss input capacitance v gs = 0v, v ds = 25v, f = 1mhz 135 pf c oss output capacitance v gs = 0v, v ds = 25v, f = 1mhz 21 pf c rss reverse transfer capacitance v gs = 0v, v ds = 25v, f = 1mhz 3.2 pf t d(on) turn-on delay v dd = 350v, i d = 1a 10 ns t r rise time v dd = 350v, i d = 1a 13.4 ns t d(off) turn-off delay v dd = 350v, i d = 1a 14.9 ns t f fall time v dd = 350v, i d = 1a 36.8 ns control section f osc switching frequency v ds = 650v, v gs = 0v 45.5 50.0 54.5 khz ? f osc switching frequency variation v gs = 10v, v gs = 0v, t c = 125c 5 10 % f fm frequency modulation 3 khz d max maximum duty cycle v fb = 4v 71 77 83 % d min minimum duty cycle v fb = 0v 0 0 0 % v start uvlo threshold voltage 11 12 13 v v stop after turn-on 7 8 9 v i fb feedback source current v fb = 0v 320 400 480 a t s/s internal soft-start time v fb = 4v 15 20 25 ms burst mode section v burh burst mode voltage t j = 25c 0.48 0.60 0.72 v v burl 0.32 0.45 0.58 v v bur(hys) 150 mv protection section i lim peak current limit t j = 25c, di/dt = 300ma/s 1.06 1.20 1.34 a t cld current limit delay time (11) 200 ns v sd shutdown feedback voltage v cc = 15v 5.5 6.0 6.5 v i delay shutdown delay current v fb = 5v 3.5 5.0 6.5 a v ovp over-voltage protection threshold v fb = 2v 22.5 24.0 25.5 v t osp output-short protection (11) threshold time t j = 25c osp triggered when t on v osp and lasts longer than t osp_fb 1.00 1.35 s v osp threshold feedback voltage 1.44 1.60 v t osp_fb feedback blanking time 2.0 2.5 s v aocp aocp voltage (11) t j = 25c 0.85 1.00 1.15 v tsd thermal shutdown (11) shutdown temperature 125 137 150 c hys tsd hysteresis 60 c t leb leading-edge blanking time (11) 300 ns continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 6 FSL116LR ? green mode fairchild power switch (fps?) electrical characteristics (continued) t a = 25 c unless otherwise specified. symbol parameter conditions min. typ. max. units total device section i op1 operating supply current (11) (while switching) v cc = 14v, v fb > v burh 2.5 3.5 ma i op2 operating supply current (control part only) v cc = 14v, v fb < v burl 1.8 2.5 ma i ch startup charging current v cc = 0v 0.9 1.1 1.3 ma v str minimum v str supply voltage v cc = v fb = 0v, v str increase 35 v note: 11. though guaranteed by design, it is not 100% tested in production.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 7 FSL116LR ? green mode fairchild power switch (fps?) typical performance characteristics these characteristic graphs are normalized at t a =25. 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 operating frequency (f osc ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 maximum duty cycle (d max ) figure 4. operating frequency vs. temperature figure 5. maximum duty cycle vs. temperature 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 operating supply current (i op2 ) 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 start threshold voltage (v start ) figure 6. operating supply current vs. temperature figure 7. start threshold voltage vs. temperature 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 stop threshold voltage (v stop ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 feedback source current (i fb ) figure 8. stop threshold voltage vs. temperature figure 9. feedback source current vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 8 FSL116LR ? green mode fairchild power switch (fps?) typical performance characteristics (continued) these characteristic graphs are normalized at t a =25. 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 startup charging current (i ch ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 peak current limit (i lim ) figure 10. startup charging current vs. temperature figure 11. peak current limit vs. temperature 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 burst operating supply current (i op1 ) 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -40 -25 0 25 50 75 100 120 140 over-voltage protection (v ovp ) figure 12. burst operating supply current vs. temperature figure 13. over-voltage protection vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 9 FSL116LR ? green mode fairchild power switch (fps?) functional description startup at startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (c a ) connected with the v cc pin, as illustrated in figure 14. when v cc reaches the start voltage of 12v, the fps? begins switching and the internal high- voltage current source is di sabled. the fps continues normal switching operation and the power is provided from the auxiliary transformer winding unless v cc goes below the stop voltage of 8v. figure 14. startup circuit oscillator block the oscillator frequency is set internally and the fps has a random frequency fluctuat ion function. fluctuation of the switching frequency of a switched power supply can reduce emi by spreading the energy over a wider frequency range than the bandwid th measured by the emi test equipment. the amount of emi reduction is directly related to the r ange of the frequency variation. the range of frequency variation is fixed internally; however, its selection is randomly chosen by the combination of external feedback voltage and internal free-running oscillator. this randomly chosen switching frequency effectively spreads the emi noise nearby switching frequency and allows the use of a cost- effective inductor instead of an ac input line filter to satisfy the world-wide emi requirements. figure 15. frequency fluctuation waveform feedback control FSL116LR employs current-mode control, as shown in figure 16. an opto-coupler (such as the fod817a) and shunt regulator (such as t he ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the r sense resistor makes it possible to control the switching duty cycle. when the shunt regul ator reference pin voltage exceeds the internal refer ence voltage of 2.5v, the opto- coupler led current incr eases, the feedback voltage v fb is pulled down, and the duty cycle is reduced. this typically occurs when the input voltage is increased or the output load is decreased. figure 16. pulse-width-modulation circuit leading-edge blanking (leb) at the instant the internal sensefet is turned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically cause a high-current spike through the sensefet. excessive voltage across the r sense resistor leads to incorrect feedback operation in the current-mode pwm control. to counter this effect, the fps employs a leading-edge blanking (leb) circuit ( see the figure 16 ). this circuit inhibits the pwm comparator for a short time (t leb ) after the sensefet is turned on. protection circuits the fps has several protective functions, such as overload protection (olp), over-voltage protection (ovp), output-short protec tion (osp), under-voltage lockout (uvlo), abnormal over-current protection (aocp), and thermal shutdow n (tsd). because these various protection circuits ar e fully integrated in the ic without external components, the reliability is improved without increasing cost. once a fault condition occurs, switching is terminated and the sensefet remains off. this causes v cc to fall. when v cc reaches the uvlo stop voltage, v stop (8v), the protection is reset and the internal high-voltage current source charges the v cc capacitor via the v str pin. when v cc reaches the uvlo start voltage, v start (12v), the fps resumes normal operation. in this manner , the auto-restart can alternately enable and disabl e the switching of the power sensefet until the faul t condition is eliminated.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 10 FSL116LR ? green mode fairchild power switch (fps?) figure 17. auto-restart protection waveforms overload protection (olp) overload is defined as the load current exceeding a pre- set level due to an unexpected event. in this situation, the protection circuit should be activated to protect the smps. however, even w hen the smps is operating normally, the overload protection (olp) circuit can be activated during the load transit ion or startup. to avoid this undesired operation, the olp circuit is designed to be activated after a specified time to determine whether it is a transient situation or a true overload situation. in conjunction with the i pk current limit pin (if used), the current-mode feedback path limit s the current in the sensefet when the maximum pwm duty cycle is attained. if the output c onsumes more than this maximum power, the output voltage (v o ) decreases below its rating voltage. th is reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor curr ent, thus increasing the feedback voltage (v fb ). if v fb exceeds 2.4v, the feedback input diode is blo cked and the 5a current source (i delay ) starts to charge c fb slowly up to v cc . in this condition, v fb increases until it reaches 6v, when the switching operation is terminated, as shown in figure 18. the shutdown delay is the time required to charge c fb from 2.4v to 6v with 5a current source. figure 18. overload protection (olp) abnormal over-current protection (aocp) when the secondary rectifier diodes or the transformer pin are shorted, a steep current with extremely high di/dt can flow through the sensefet during the leb time. even though the fps has olp (overload protection), it is not enough to protect the fps in that abnormal case, since severe current stress is imposed on the sensefet until olp triggers. the fps includes the internal aocp (abnormal over-current protection) circuit shown in figure 19. when the gate turn-on signal is applied to the power sensefet, the aocp block is enabled and monitors the curr ent through the sensing resistor. the voltage across the resistor is compared with a preset aocp level. if the sensing resistor voltage is greater than the aocp leve l, the set signal is applied to the latch, resulting in the shutdown of the smps. figure 19. abnormal over-current protection thermal shutdown (tsd) the sensefet and the cont rol ic are integrated, making it easier to detect the temperature of the sensefet. when the temperature exceeds approximately 137c, thermal shutdown is activated. over-voltage protection (ovp) in the event of a malfunc tion in the secondary-side feedback circuit or an open feedback loop caused by a soldering defect, the current through the opto-coupler transistor becomes almost zero. then, v fb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the smps until the overload protection is activated. because excess energy is provided to the output, the output voltage may exceed the ra ted voltage before the overload protection is acti vated, resulting in the breakdown of the devices in the secondary side. to prevent this situation, an over-voltage protection (ovp) circuit is employed. in general, v cc is proportional to the output voltage and the fps uses v cc instead of directly monitoring the output voltage. if v cc exceeds 24v, ovp circuit is activated, resu lting in termination of the switching operation. to av oid undesired activation of ovp during normal operation, v cc should be designed to be below 24v.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 11 FSL116LR ? green mode fairchild power switch (fps?) output-short protection (osp) if the output is shorted, st eep current with extremely high di/dt can flow through the sensefet during the leb time. such a steep current brings high-voltage stress on the drain of sensefet when turned off. to protect the device from such an abnormal condition, osp detects v fb and sensefet turn-on time. when the v fb is higher than 1.6v and t he sensefet turn-on time is lower than 1.0s, the fps recognizes this condition as an abnormal error and shuts down pwm switching until v cc reaches v start again. an abnormal condition output is shown in figure 20. figure 20. output short waveforms (osp) soft-start the fps has an internal soft-start circuit that slowly increases the feedback volt age, together with the sensefet current, after it starts. the typical soft-start time is 20ms, as shown in figure 21, where progressive increments of the sensefet current are allowed during the startup phase. the pul se width to the power switching device is progressi vely increased to establish the correct working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressively increased with the intention of smoothly establishing t he required output voltage. soft-start helps to prevent transformer saturation and reduce the stress on the secondary diode. 1.25ms 16 steps current limit i lim t 0.25i lim drain current figure 21. internal soft-start burst operation to minimize power dissipation in standby mode, the fps enters burst mode. as the load decreases, the feedback voltage decreases. as shown in figure 22, the device automatically ent ers burst mode when the feedback voltage drops below v burh . switching continues, but the current limit is fixed internally to minimize flux density in the transformer. the fixed current limit is larger than that defined by v fb = v burh and, therefore, v fb is driven down further. switching continues until the feedba ck voltage drops below v burl . at this point, switching stops and the out put voltages start to drop at a rate dependent on the standby current load. this causes the feedba ck voltage to rise. once it passes v burh , switching resumes. the feedback voltage then falls and the proce ss repeats. burst mode alternately enables and dis ables switching of the sensefet and reduces switching loss in standby mode. figure 22. burst-mode operation adjusting peak current limit as shown in figure 23, a combined 6k ? internal resistance is connected to the non-inverting lead on the pwm comparator. an external resistance of rx on the current limit pin forms a par allel resistance with the 6k ? when the internal diodes are biased by the main current source of 400a. for example, FSL116LR has a typical sensefet peak current limit (i lim ) of 1.2a. i lim can be adjusted to 0.8a by in serting rx between the i pk pin and the ground. the value of the rx can be estimated by the following equations: xk : 6k 0.8a : 1.2a = (1) 6k || rx x = (2) where x is the resistance of the parallel network. figure 23. peak current limit adjustment
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 12 physical dimensions 5.08 max 0.33 min 2.54 7.62 0.56 0.355 1.65 1.27 3.683 3.20 3.60 3.00 6.67 6.096 9.83 9.00 7.62 9.957 7.87 0.356 0.20 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and toleranc es per asme y14.5m-1994 8.255 7.61 e) drawing filename and revsion: mkt-n08frev2. (0.56) figure 24. 8-lead, dual inline package (dip) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FSL116LR ? rev. 1.0.1 13 FSL116LR ? green mode fairchild power switch (fps?)

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